This invention relates to in-circuit digital testers. More particular, the invention relates to a circuit for generating test signals for testing bus oriented electronic devices and components, such as microprocessor boards.
As used herein, an in-circuit digital tester refers to a tester that is capable of testing components in devices in a circuit without regard to whether or not the electrical node into which a test signal is applied is connected to the output of another logic device. In-circuit testers are capable of generating and applying a digital test signal to an output node of a logic device that is normally at a logic ground to cause that output to go to a logic high without damaging the device. In other words, the use of the term "in-circuit" means that the device or circuit under test does not have to be isolated or removed from the surrounding circuits in order to apply digital test signals and to monitor its outputs.
Prior-art in-circuit digital testers, such as that disclosed in U.S. Pat. No. 4,216,539, entitled "In-Circuit Digital Tester," provides a programmed memory digital test signal generator associated with each pin in a bed of nails fixture. The test signal generators are capable of generating a wide variety of digital test signals to test components or devices in a circuit under test. (U.S. Pat. No. 4,216,539 is incorporated herein for all purposes.) Some components, however, require an especially complexed test signal pattern generation in order to adequately test the electrical performance characteristics of the component. One such component is a microprocessor chip.
Microprocessors are bus oriented devices. To test a microprocessor chip requires the generation of multi-lined data bus signals. These bus signals usually represent either data or memory addresses. In addition, to properly exercise or set up a data bus signal generation sequence, a sequence of control signals must either precede or be generated concurrently with the data bus signals before the microprocessor can properly execute its internal sequences. Microprocessors execute their instructions using repeated selected signal sequences, such as an instruction fetch cycle, a read from memory cycle, a write to memory cycle, etc. To test microprocessors, complex and lengthy test patterns generated simultaneously at a plurality of input and output points of the circuit are required. This requirement of complex test patterns simultaneously at several input points is true for other logic devices, such as UARTs, programmed I/O devices, etc.
Testing of a microprocessor and the devices associated therewith, i.e., a microprocessor board, is best accomplished by simulating the operations of the microprocessor programmed in a specific manner. In this way, operations of the microprocessor can be checked, and by making the microprocessor function in a specific manner through execution of its own instructions, external devices, such as RAM and ROM memories connected to the microprocessor's bus can also be tested. But, to accomplish this task using prior-art stored memory test signal generators to generate the test signals would require an unmanageable and cost prohibitive amount of programmable memory in each test signal generator.
To solve the problem of generating these complexed test signal patterns while utilizing the advantages and novelty over the prior-art for in-circuit digital testers offered by the invention disclosed in the application incorporated above, the present invention has segregated the test signals for bus oriented devices into two categories--data bus sequences of test signals and protocol control sequences of test signals.
The data bus test signals are applied as parallel words onto the multi-lined data buses. When testing a microprocessor device this data will represent either data or memory addresses. A data sequence of data bus signals is defined according to the present invention as a sequence of signals generated from the programmable memory test signal generators associated with the data bus, starting at a predetermined starting address and ending at a predetermined last address.
For certain logic devices, such as microprocessors, a plurality of individual control signals are required in parallel and timed relationship to each other such that when all the control signals are viewed in parallel, they define a protocol sequence of control test signals which communicate to a device information necessary for the device to perform a normally intended function. For the present invention, the protocol control sequences of control test signals are defined by a starting and a last address of the programmable memory associated with the digital test signal generators which generate the control signals. From these predefined protocol and data sequences, all of the functions of the device may be exercised by recursively generating the sequences as required to test each function of the device by specifying the starting and last addresses for each sequence.